Design and optimization of low-power SAR ADC

Abstract

In the era of Internet-of-Things (IoT) and wearable biomedical technologies, the need for ultra-low-power analog-to-digital converters (ADCs) is increasingly critical. These systems often interface with low-activity signals such as electrocardiograms (ECG), voice, and ultrasonic data, which exhibit sparse changes over time. This thesis presents a set of novel design methodologies for energy-efficient successive approximation register (SAR) ADCs that leverage the statistical characteristics and temporal correlations of low-activity signals to reduce power consumption across the comparator, digital-to-analog converter (DAC), and digital control logic. To minimize comparator activity, various search schemes were developed. These include adaptive search algorithms based on first- and second-order differences, as well as machine-learning (ML) and reinforcement-learning (RL)-based methods. The proposed algorithms dynamically reduce the number of bit comparisons from the fixed N cycles in conventional N-bit SAR ADCs to a range between 2 and N, resulting in up to 79.74% reduction in comparator activity compared to the monotonic method, while maintaining the same conversion accuracy. To further reduce DAC switching energy, this thesis introduces a novel DAC update scheme specifically designed for low-activity signals. These approaches achieve up to 88.88% reduction in switching energy compared to the monotonic method. In addition, a dedicated digital logic cell design using different techniques is proposed, reducing short-circuit power in the SAR logic and offering up to 34.77% improvement in digital logic energy efficiency. The proposed techniques were validated through MATLAB simulations, circuit-level implementation, and silicon measurements in a 0.18 ?m CMOS process. Measurement results from a fabricated 10-bit SAR ADC chip demonstrate a 70.05% reduction in comparator activity compared to the conventional monotonic approach. With a 5.6 kHz sinusoidal input, the ADC achieves an SNDR of 57.78 dB and SFDR of 67.06 dB. The total power dissipation remains below 0.54 ?W, with an additional estimated 0.22 ?W for the digital part, making it an ideal solution for always-on voice interfaces in battery-operated IoT and biomedical devices. Overall, this thesis contributes a comprehensive suite of techniques for next-generation low-power SAR ADCs, balancing architectural innovation, machine learning intelligence, and circuit-level optimization.