Performance limitations of block-multithreaded distributed-memory systems

dc.contributor.author	Zuberek, W. M.
dc.date.issued	2009-12
dc.description.abstract	The performance of modern computer systems is increasingly often limited by long latencies of accesses to the memory subsystems. Instruction-level multithreading is an architectural approach to tolerating such long latencies by switching instruction threads rather than waiting for the completion of memory operations. The paper studies performance limitations in distributed-memory block multithreaded systems and determines conditions for such systems to be balanced. Event-driven simulation of a timed Petri net model of a simple distributed-memory system confirms the derived performance results
dc.identifier.doi	http://dx.doi.org/10.1109/WSC.2009.5429718
dc.identifier.uri	http://dx.doi.org/10.1109/WSC.2009.5429718
dc.identifier.uri	https://hdl.handle.net/20.500.14783/14645
dc.language.iso	en
dc.relation.uri	https://www.mun.ca/
dc.title	Performance limitations of block-multithreaded distributed-memory systems
dc.type	conference_item
mem.campus	St. John's Campus
mem.department	Computer Science
mem.divisions	CompSci
mem.eventDates	13-16 December, 2009
mem.eventLocation	Austin, TX, USA
mem.eventTitle	2009 Winter Simulation Conference (WSC)
mem.eventType	conference
mem.fullTextStatus	public
mem.isPublished	pub
mem.presType	paper
mem.refereed	True

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